1. Field of the Invention
The present invention relates to a TDMA processing apparatus suitable for use in communication equipment of a TDMA system.
2. Description of the Related Art
FIG. 1 is a block diagram showing a conventional TDMA processing apparatus. The TDMA processing apparatus is used to supply given control signals to peripheral devices such as a modulator and demodulator, a transmit-receive unit, a frequency synthesizer, etc. in given timing. In FIG. 1 , there are shown a counter for counting input reference clock pulses, a memory 2 for specifying an address in response to the count of the counter 1, and an output buffer 3 for supplying data output from the memory 2 to each of the peripheral devices under the control of an external device. The elements 1, 2 and 3 are connected to peripheral devices to form a complete communication transmitter/receiver. The peripheral devices typical in such prior art TDMA communication transmitter/receiver are shown in block 4. These include a modulator 4a, a transmitter 4b, a frequency synthesizer 4c, a demodulator 4d, a receiver 4e and a duplexer 4f. An antenna 5 is typically connected to the system through the duplexer 4f.
FIG. 2 shows frame and burst structures employed in a TDMA system based on the EIA IS-54 standard. The frame structure will now be described below by way of example. Let's now assume that three slots represent one frame, one slot is made up of m bits and the time needed to transmit one frame is n seconds. Incidentally, an "SACCH", a "DATA", a "CDVCC", a "RSV", a "SYNC", a "G", and a "R" represent a slow-speed type attached control channel, a voice channel or a high-speed type attached control channel, a coded identification color code, a reserve area, a synchronizing word, a guard time interval, and a lamp time interval, respectively.
In this case, the data transfer rate is 3 m/n (bits/second), and the transfer time per bit is n/3 m (seconds). In order to reliably carry out the operation of each of the peripheral devices, it is necessary to perform the timing control for supplying a control signal to each of the peripheral devices at a time interval shorter than the transfer time per bit. If the time interval referred to above is one-xth the transfer time per bit, then the timing control makes it necessary to be carried out at a time interval of n/3 mx (seconds).
The operation of the TDMA processing apparatus will now be described below. From the above description, the period of the reference clock pulses becomes n/3 mx. The counter 1 counts the reference clock pulses. When one clock pulse is input to the counter 1 at the time that the count of (3 mx-1) is reached, the counter 1 develops the count 0. That is, the counter 1 circularly counts at 3 mx indicative of the number of control timings in one frame. The width of the output from the counter 1 is log.sub.2 3 mx bits, and its output is input to a desired address in the memory 2.
Let's now consider that the control signals supplied to the peripheral devices are classified into y types. In this case, the memory 2 is organized as shown in FIG. 3 so that the contents of 3 mx words (one word being made up of y bits) in total can be stored. In addition, data of y bits, which has been stored at an address specified by the output of the counter 1, is delivered to the output buffer 3.
The output buffer 3 is supplied with output control signals each indicative of either output permission or output nonpermission corresponding to each bit. The output buffer 3 now supplies to a desired peripheral device, data of each bit corresponding to the output permission, of data input thereto. Thus, the output buffer 3 delivers control signals to the peripheral devices for each frame cycle at a rate x times the data transfer rate. Incidentally, the control signals represent an instruction for the changeover of a frequency of the frequency synthesizer and an instruction for starting up or disabling the transmit-receive unit, for example.
The conventional TDMA processing apparatus constructed as described above needs the memory 2 having the capacity proportional to the number of bits per frame, i.e., 3 m. Since the width of data in a memory element is normally either 8 bits or 16 bits, memory elements represented in the form of required data width y/data width of memory element (number) are needed. In addition, a large number of memory elements should be provided as the memory 2 as the number of the control signals fed to the peripheral devices increases, thereby causing the problem that circuits employed in the TDMA processing apparatus should be designed on a large scale, and the manufacturing cost of the TDMA processing apparatus becomes expensive.
Incidentally, the conventional TDMA processing apparatus has been disclosed in Japanese Patent Application Laid-Open No. 60-16740.